1. Field of Invention
The present invention relates in general to integrated circuits and in particular, to a system-on-a-chip with soft cache and systems and methods using the same.
2. Background of Invention
Handheld personal electronic appliances have become increasingly popular as new technologies have produced affordable devices with a high degree of functionality. One such device is the portable digital audio player, which downloads digital audio data, stores those data in a read-writeable memory, and converts those data into audio on user demand. The digital data is downloaded from a network or retrieved from a fixed medium, such as a compact disk, in one of several forms, including the MPEG Layer 3, ACC, and MS Audio protocols. An audio decoder, supported by appropriate firmware, retrieves the encoded data from memory, applies the corresponding decoding algorithm and coverts the decoded data into analog form for driving a headset or other portable speaker system.
The use of systems-on-a-chip in the design and construction of handheld digital music players allows all the requisite functionality to be contained in a compact, relatively inexpensive unit. Notwithstanding, the integration of the major functions of a digital music player into a single chip device is not a trivial task. Not only must the device include the processing power capable of performing digital to audio conversion efficiently, it must also be capable of interfacing with various sources of digitally encoded data, support different user I/O options, such as LCD displays and headphones, and operate in conjunction with sufficiently large on-chip and off-chip memory spaces storing (programming code and data) needed to produce high-quality audio.
According to the inventive concepts, a cache system is disclosed which compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in a programmable cache memory space. A cache line size of the cache line is also programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding programmable soft cache space in memory address by block address bits from the virtual address.
Systems and software embodying the principles of the present invention advantageously allow software caching in systems with limited or no hardware caching support. An example is the disclosed system-on-a-chip employing an ARM7tdmi CPU core, which has neither a hardware cache nor a memory management unit. Additionally, since cache line replacement is done in software on a cache miss, the interface between memories operating under different protocols has increased efficiency.